LINEMULT=B_0x0, FORMAT=B_0x0, SWAPRB=B_0x0, DBM=B_0x0, LMAWM=B_0x0, LMAWE=B_0x0
DCMIPP Pipe2 pixel packer configuration register
| FORMAT | Memory format (only coplanar formats are supported in Pipe2) 0 (B_0x0): RG/B888 or YUV444 1-buffer 1 (B_0x1): RGB565 1-buffer 2 (B_0x2): ARGB8888 3 (B_0x3): RGBA8888 4 (B_0x4): monochrome Y8 or G8 1-buffer 5 (B_0x5): YUV444 1-buffer (FOURCC = AYUV) 6 (B_0x6): YUV422 1-buffer (FOURCC = YUYV) |
| SWAPRB | Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components 0 (B_0x0): No swap of R-vs-B (U-vs-V) 1 (B_0x1): Swap active. |
| LINEMULT | Amount of capture completed lines for LINE event and interrupt 0 (B_0x0): Event after every line 1 (B_0x1): Event after two lines 2 (B_0x2): Event after four lines 3 (B_0x3): Event after eight lines 4 (B_0x4): Event after sixteen lines 5 (B_0x5): Event after 32 lines 6 (B_0x6): Event after 64 lines 7 (B_0x7): Event after 128 lines |
| DBM | Double buffer mode 0 (B_0x0): No double buffer mode activated. Pipe2 is always dump to memory address set by DCMIPP_P2PPM0AR1 1 (B_0x1): Double buffer mode activated. Dump address location switches from DCMIPP_P2PPM0AR1 register to DCMIPP_P2PPM0AR2 register alternatively on each frame |
| LMAWM | Line multi address wrapping modulo 0 (B_0x0): Wraps address after every line 1 (B_0x1): Wraps address after two lines 2 (B_0x2): Wraps address after four lines 3 (B_0x3): Wraps address after eight lines 4 (B_0x4): Wraps address after sixteen lines 5 (B_0x5): Wraps address after 32 lines 6 (B_0x6): Wraps address after 64 lines 7 (B_0x7): Wraps address after 128 lines |
| LMAWE | Line multi address wrapping enable bit 0 (B_0x0): Line multi address wrapping disabled. 1 (B_0x1): Line multi address wrapping enabled. |