stm32 /stm32n6 /STM32N655 /DMA2D /DMA2D_CR

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Interpret as DMA2D_CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (START)START 0 (B_0x0)SUSP 0 (B_0x0)ABORT 0 (B_0x0)LOM 0 (B_0x0)TEIE 0 (B_0x0)TCIE 0 (B_0x0)TWIE 0 (B_0x0)CAEIE 0 (B_0x0)CTCIE 0 (B_0x0)CEIE 0 (B_0x0)MODE

LOM=B_0x0, CTCIE=B_0x0, TCIE=B_0x0, TEIE=B_0x0, CAEIE=B_0x0, SUSP=B_0x0, ABORT=B_0x0, TWIE=B_0x0, CEIE=B_0x0, MODE=B_0x0

Description

DMA2D control register

Fields

START

Start

SUSP

Suspend

0 (B_0x0): Transfer not suspended

1 (B_0x1): Transfer suspended

ABORT

Abort

0 (B_0x0): No transfer abort requested

1 (B_0x1): Transfer abort requested

LOM

Line offset mode

0 (B_0x0): Line offsets expressed in pixels

1 (B_0x1): Line offsets expressed in bytes

TEIE

Transfer error (TE) interrupt enable

0 (B_0x0): TE interrupt disabled

1 (B_0x1): TE interrupt enabled

TCIE

Transfer complete (TC) interrupt enable

0 (B_0x0): TC interrupt disabled

1 (B_0x1): TC interrupt enabled

TWIE

Transfer watermark (TW) interrupt enable

0 (B_0x0): TW interrupt disabled

1 (B_0x1): TW interrupt enabled

CAEIE

CLUT access error (CAE) interrupt enable

0 (B_0x0): CAE interrupt disabled

1 (B_0x1): CAE interrupt enabled

CTCIE

CLUT transfer complete (CTC) interrupt enable

0 (B_0x0): CTC interrupt disabled

1 (B_0x1): CTC interrupt enabled

CEIE

Configuration error (CE) interrupt enable

0 (B_0x0): CE interrupt disabled

1 (B_0x1): CE interrupt enabled

MODE

DMA2D mode

0 (B_0x0): Memory-to-memory (FG fetch only)

1 (B_0x1): Memory-to-memory with PFC (FG fetch only with FG PFC active)

2 (B_0x2): Memory-to-memory with blending (FG and BG fetch with PFC and blending)

3 (B_0x3): Register-to-memory (no FG nor BG, only output stage active)

4 (B_0x4): Memory-to-memory with blending and fixed color FG (BG fetch only with FG and BG PFC active)

5 (B_0x5): Memory-to-memory with blending and fixed color BG (FG fetch only with FG and BG PFC active)

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