Regviz

stm32 /stm32n6 /STM32N655 /DTS /DTS_TSCSDIFSMPLCLRR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DTS_TSCSDIFSMPLCLRR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/DTS/DTS_TSCSDIFSMPLCLRR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SMPL_CNTER_CLEAR

SMPL_CNTER_CLEAR=B_0x0

Description

DTS TSC sample clear register

Fields

SMPL_CNTER_CLEAR

Sample counter clear bit

0 (B_0x0): Counter value not cleared

1 (B_0x1): Counter value cleared

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32