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stm32 /stm32n6 /STM32N655 /DTS /DTS_TSCSDIF_CFGR

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Interpret as DTS_TSCSDIF_CFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SDIF_INHIBIT

SDIF_INHIBIT=B_0x0

Description

DTS TSC SDIF control register

Fields

SDIF_INHIBIT

Serial data interface (SDIF) programming inhibit

0 (B_0x0): No Inhibition

1 (B_0x1): TS0 inhibited/TS1 serial programming activated (SPA)

2 (B_0x2): TS1 inhibited/TS0 serial programming activated (SPA)

3 (B_0x3): TS1 and TS0 inhibited

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32