stm32 /stm32n6 /STM32N655 /ETH /ETH_DMAA4RXACR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ETH_DMAA4RXACR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDWC0RPC0RHC0RDC

Description

AXI4 receive channel ACE control register

Fields

RDWC

Receive DMA Write Descriptor Cache Control

RPC

Receive DMA Payload Cache Control

RHC

Receive DMA Header Cache Control

RDC

Receive DMA Buffer Cache Control

Links

()