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stm32 /stm32n6 /STM32N655 /ETH /ETH_DMAA4TXACR

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Interpret as ETH_DMAA4TXACR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TDRC0TEC0THC

Description

AXI4 transmit channel ACE control register

Fields

TDRC

Transmit DMA Read Descriptor Cache Control
TEC

Transmit DMA Extended Packet Buffer or TSO Payload Cache Control
THC

Transmit DMA First Packet Buffer or TSO Header Cache Control

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32