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stm32 /stm32n6 /STM32N655 /ETH /ETH_DMAC1RXIWTR

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Interpret as ETH_DMAC1RXIWTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RWT0 (B_0x0)RWTU

RWTU=B_0x0

Description

Channel 1 R1 interrupt watchdog timer register

Fields

RWT

Receive Interrupt Watchdog Timer Count
RWTU

Receive Interrupt Watchdog Timer Count Units

0 (B_0x0): 256

1 (B_0x1): 512

2 (B_0x2): 1024

3 (B_0x3): 2048

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32