stm32 /stm32n6 /STM32N655 /ETH /ETH_DMADSR

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Interpret as ETH_DMADSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AXWHSTS)AXWHSTS 0 (AXRHSTS)AXRHSTS 0 (B_0x0)RPS00 (B_0x0)TPS00RPS10TPS1

RPS0=B_0x0, TPS0=B_0x0

Description

Debug status register

Fields

AXWHSTS

AXI Master Write Channel

AXRHSTS

AXI Master Read Channel Status

RPS0

DMA Channel 0 Receive Process State

0 (B_0x0): Stopped (Reset or Stop Receive Command issued)

1 (B_0x1): Running (Fetching Rx Transfer Descriptor)

3 (B_0x3): Running (Waiting for Rx packet)

4 (B_0x4): Suspended (Rx Descriptor Unavailable)

5 (B_0x5): Running (Closing the Rx Descriptor)

6 (B_0x6): Timestamp write state

7 (B_0x7): Running (Transferring the received packet data from the Rx buffer to the system memory)

TPS0

DMA Channel 0 Transmit Process State

0 (B_0x0): Stopped (Reset or Stop Transmit Command issued)

1 (B_0x1): Running (Fetching Tx Transfer Descriptor)

2 (B_0x2): Running (Waiting for status)

3 (B_0x3): Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))

4 (B_0x4): Timestamp write state

6 (B_0x6): Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)

7 (B_0x7): Running (Closing Tx Descriptor)

RPS1

DMA Channel 1 Receive Process State

TPS1

DMA Channel 1 Transmit Process State

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