TXFIFOSIZE=B_0x0, RXFIFOSIZE=B_0x0, L3L4FNUM=B_0x0, ADDR64=B_0x0, HASHTBLSZ=B_0x0
HW feature 1 register
| RXFIFOSIZE | MTL Receive FIFO Size 0 (B_0x0): 128 bytes 1 (B_0x1): 256 bytes 2 (B_0x2): 512 bytes 3 (B_0x3): 1,024 bytes 4 (B_0x4): 2,048 bytes 5 (B_0x5): 4,096 bytes 6 (B_0x6): 8,192 bytes 7 (B_0x7): 16,384 bytes 8 (B_0x8): 32 Kbytes 9 (B_0x9): 64 Kbytes 10 (B_0xA): 128 Kbytes 11 (B_0xB): 256 Kbytes |
| SPRAM | Single Port RAM Enable |
| TXFIFOSIZE | MTL Transmit FIFO Size 0 (B_0x0): 128 bytes 1 (B_0x1): 256 bytes 2 (B_0x2): 512 bytes 3 (B_0x3): 1,024 bytes 4 (B_0x4): 2,048 bytes 5 (B_0x5): 4,096 bytes 6 (B_0x6): 8,192 bytes 7 (B_0x7): 16,384 bytes 8 (B_0x8): 32 Kbytes 9 (B_0x9): 64 Kbytes 10 (B_0xA): 128 Kbytes |
| OSTEN | One-Step Timestamping Enable |
| PTOEN | PTP Offload Enable |
| ADVTHWORD | IEEE 1588 High Word Register Enable |
| ADDR64 | Address width 0 (B_0x0): 32 bits |
| DCBEN | DCB Feature Enable |
| SPHEN | Split Header Feature Enable |
| TSOEN | TCP Segmentation Offload Enable |
| DBGMEMA | DMA Debug Registers Enable |
| AVSEL | AV Feature Enable |
| RAVSEL | Rx Side Only AV Feature Enable |
| POUOST | One Step for PTP over UDP/IP Feature Enable |
| HASHTBLSZ | Hash Table Size 0 (B_0x0): No Hash table 1 (B_0x1): 64 2 (B_0x2): 128 3 (B_0x3): 256 |
| L3L4FNUM | Total number of L3 or L4 Filters 0 (B_0x0): No L3 or L4 Filter 1 (B_0x1): 1 L3 or L4 Filter 2 (B_0x2): 2 L3 or L4 Filters 8 (B_0x8): 8 L3 or L4 |