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stm32 /stm32n6 /STM32N655 /ETH /ETH_MACLMIR

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Interpret as ETH_MACLMIR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LSI0 (B_0x0)DRSYNCR 0LMPDRI

DRSYNCR=B_0x0

Description

Log message interval register

Fields

LSI

Log Sync Interval
DRSYNCR

Delay_Req to SYNC Ratio

0 (B_0x0): DelayReq generated for every received SYNC

1 (B_0x1): DelayReq generated every alternate reception of SYNC
LMPDRI

Log Min Pdelay_Req Interval

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32