Regviz

stm32 /stm32n6 /STM32N655 /ETH /ETH_MACPHYCSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ETH_MACPHYCSR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/ETH/ETH_MACPHYCSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TC)TC 0 (B_0x0)LUD 0 (B_0x0)LNKMOD 0 (B_0x0)LNKSPEED 0 (B_0x0)LNKSTS

LNKSTS=B_0x0, LUD=B_0x0, LNKSPEED=B_0x0, LNKMOD=B_0x0

Description

PHYIF control status register

Fields

TC

Transmit Configuration in RGMII
LUD

Link Up or Down

0 (B_0x0): Link Down

1 (B_0x1): Link Up
LNKMOD

Link Mode

0 (B_0x0): Half-duplex mode

1 (B_0x1): Full-duplex mode
LNKSPEED

Link Speed

0 (B_0x0): 2.5 MHz

1 (B_0x1): 25 MHz

2 (B_0x2): 125 MHz
LNKSTS

Link Status

0 (B_0x0): Link down

1 (B_0x1): Link up

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32