TRGTMODSEL0=B_0x0, MCGREN0=B_0x0
PPS control register
| PPSCTRL | PPS Output Frequency Control 1 (B_0x1): The binary rollover is 2 Hz, and the digital rollover is 1 Hz. 2 (B_0x2): The binary rollover is 4 Hz, and the digital rollover is 2 Hz. 3 (B_0x3): The binary rollover is 8 Hz, and the digital rollover is 4 Hz. 4 (B_0x4): The binary rollover is 16 Hz, and the digital rollover is 8 Hz. 15 (B_0xF): The binary rollover is 32.768 KHz and the digital rollover is 16.384 KHz. |
| PPSEN0 | Flexible PPS Output Mode Enable |
| TRGTMODSEL0 | Target Time Register Mode for PPS Output 0 (B_0x0): Target Time registers are programmed only for generating the interrupt event. 1 (B_0x1): Enables MCGR Interrupt whose status bit is indicated by TSTARGT0 bit in Timestamp status register (ETH_MACTSSR) register 2 (B_0x2): Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS output signal generation. 3 (B_0x3): Target Time registers are programmed only for starting or stopping the PPS output signal generation. No interrupt is asserted. |
| MCGREN0 | MCGR Mode Enable for PPS0 Output 0 (B_0x0): PPS mode 1 (B_0x1): MCGR mode |
| TIMESEL | Time Select |