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stm32 /stm32n6 /STM32N655 /ETH /ETH_MACQ0TXFCR

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Interpret as ETH_MACQ0TXFCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FCB_BPA)FCB_BPA 0 (TFE)TFE 0 (B_0x0)PLT0 (DZPQ)DZPQ 0PT

PLT=B_0x0

Description

Tx Queue 0 flow control register

Fields

FCB_BPA

Flow Control Busy or Backpressure Activate
TFE

Transmit Flow Control Enable
PLT

Pause Low Threshold

0 (B_0x0): Pause Time minus 4 Slot Times (PT -4 slot times)

1 (B_0x1): Pause Time minus 28 Slot Times (PT -28 slot times)

2 (B_0x2): Pause Time minus 36 Slot Times (PT -36 slot times)

3 (B_0x3): Pause Time minus 144 Slot Times (PT -144 slot times)

4 (B_0x4): Pause Time minus 256 Slot Times (PT -256 slot times)

5 (B_0x5): Pause Time minus 512 Slot Times (PT -512 slot times)
DZPQ

Disable Zero-Quanta Pause
PT

Pause Time

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32