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stm32 /stm32n6 /STM32N655 /ETH /ETH_MACRXQC0R

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ETH_MACRXQC0R

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https://regviz.com/r/stm32/stm32n6/STM32N645/ETH/ETH_MACRXQC0R#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RXQ0EN 0 (B_0x0)RXQ1EN

RXQ1EN=B_0x0, RXQ0EN=B_0x0

Description

Rx queue control 0 register

Fields

RXQ0EN

Receive Queue 0 Enable

0 (B_0x0): Not enabled

1 (B_0x1): Queue 0 enabled for AV

2 (B_0x2): Queue 0 enabled for Generic traffic
RXQ1EN

Receive Queue 1 Enable

0 (B_0x0): Not enabled

1 (B_0x1): Queue 1 enabled for AV

2 (B_0x2): Queue 1 enabled for Generic traffic

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32