stm32 /stm32n6 /STM32N655 /ETH /ETH_MAC_IACR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ETH_MAC_IACR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OB)OB 0 (B_0x0)COM 0 (B_0x0)AUTO 0 (B_0x0)AOFF0 (B_0x0)MSEL

AOFF=B_0x0, MSEL=B_0x0, AUTO=B_0x0, COM=B_0x0

Description

MAC Indirect Access Control register

Fields

OB

Operation Busy.

COM

Command type

0 (B_0x0): Indicates a write operation.

1 (B_0x1): Indicates a read operation.

AUTO

Auto-increment

0 (B_0x0): AOFF is not automatically incremented. The software should program the correct address offset for each access.

1 (B_0x1): AOFF is incremented by 1. The software should ensure not to cause a wrap condition. Byte-wise read/write is not supported when auto-increment is enabled.

AOFF

Address Offset

0 (B_0x0): IndReg0 (Indirect register 0)

1 (B_0x1): IndReg1 (Indirect register 1)

7 (B_0x7): IndReg7 (Indirect register 7)

MSEL

Mode Select

0 (B_0x0): Typ_RXQ_ (Type-based RXQ mapping)

Links

()