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stm32 /stm32n6 /STM32N655 /ETH /ETH_MTLESTSR

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Interpret as ETH_MTLESTSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SWLC 0 (B_0x0)BTRE 0 (HLBF)HLBF 0 (B_0x0)HLBS 0 (B_0x0)CGCE 0 (B_0x0)SWOL 0BTRL0CGSN

SWLC=B_0x0, CGCE=B_0x0, SWOL=B_0x0, HLBS=B_0x0, BTRE=B_0x0

Description

EST Status Register

Fields

SWLC

Switch to S/W owned list Complete

0 (B_0x0): Inactive

1 (B_0x1): Active
BTRE

BTR Error

0 (B_0x0): Inactive

1 (B_0x1): Active
HLBF

Head-Of-Line Blocking due to Frame Size
HLBS

Head-Of-Line Blocking due to Scheduling

0 (B_0x0): Inactive

1 (B_0x1): Active
CGCE

Constant Gate Control Error

0 (B_0x0): Inactive

1 (B_0x1): Active
SWOL

S/W owned list

0 (B_0x0): Inactive

1 (B_0x1): Active
BTRL

BTR Error Loop Count
CGSN

Current GCL slot number

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32