Regviz

stm32 /stm32n6 /STM32N655 /ETH /ETH_MTLRXQ0MPOCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ETH_MTLRXQ0MPOCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/ETH/ETH_MTLRXQ0MPOCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0OVFPKTCNT0 (OVFCNTOVF)OVFCNTOVF 0MISPKTCNT0 (MISCNTOVF)MISCNTOVF

Description

R0 queue 0 missed packet and overflow counter register

Fields

OVFPKTCNT

Overflow Packet Counter
OVFCNTOVF

Overflow Counter Overflow Bit
MISPKTCNT

Missed Packet Counter
MISCNTOVF

Missed Packet Counter Overflow Bit

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32