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stm32 /stm32n6 /STM32N655 /ETH /ETH_MTLRXQ1CR

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Interpret as ETH_MTLRXQ1CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RXQ_WEGT 0 (RXQ_FRM_ARBIT)RXQ_FRM_ARBIT

Description

R1 queue 1 control register

Fields

RXQ_WEGT

Receive Queue Weight
RXQ_FRM_ARBIT

Receive Queue Packet Arbitration

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32