stm32 /stm32n6 /STM32N655 /FDCAN1 /FDCAN_TTMLM

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Interpret as FDCAN_TTMLM

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x00)CCM0 (B_0x0)CSS0TXEW0ENTT

CCM=B_0x00, CSS=B_0x0

Description

FDCAN TT matrix limits register

Fields

CCM

Cycle count Max

0 (B_0x00): 1 basic cycle per matrix cycle

1 (B_0x01): 2 basic cycles per matrix cycle

3 (B_0x03): 4 basic cycles per matrix cycle

7 (B_0x07): 8 basic cycles per matrix cycle

15 (B_0x0F): 16 basic cycles per matrix cycle

31 (B_0x1F): 32 basic cycles per matrix cycle

63 (B_0x3F): 64 basic cycles per matrix cycle

CSS

Cycle start synchronization

0 (B_0x0): No sync pulse

1 (B_0x1): Sync pulse at start of basic cycle

2 (B_0x2): Sync pulse at start of matrix cycle

TXEW

Tx enable window

ENTT

Expected number of Tx triggers

Links

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