BMAP0=B_0x0, FMCEN=B_0x0, CCLKEN=B_0x0, CLKDIV=B_0x0, BMAP1=B_0x0
FMC common configuration register
| CLKDIV | Clock divide ratio (for FMC_CLK signal) 0 (B_0x0): FMC_CLK period= 1x fmc_ker_ck period 1 (B_0x1): FMC_CLK period = 2 fmc_ker_ck periods 2 (B_0x2): FMC_CLK period = 3 fmc_ker_ck periods 15 (B_0xF): FMC_CLK period = 16 fmc_ker_ck periods (default value after reset) |
| CCLKEN | Continuous clock enable 0 (B_0x0): The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is defined by the programmed CLKDIV value in the FMC_BCRx register (default after reset). 1 (B_0x1): The FMC_CLK is generated continuously during asynchronous and synchronous access. |
| BMAP0 | FMC memory region mapping 0 (B_0x0): Default mapping (refer to Table 132) 1 (B_0x1): Devices are remapped (refer to Table 133) |
| BMAP1 | FMC memory region mapping 0 (B_0x0): Default mapping (refer to Table 132) 1 (B_0x1): Devices are remapped (refer to Table 133) |
| FMCEN | FMC controller enable 0 (B_0x0): FMC controller disabled 1 (B_0x1): FMC controller enabled |