DMADEN=B_0x0, ACYNBR=B_0x0, CMD2T=B_0x0, CMD1T=B_0x0, CMD2EN=B_0x0
FMC NAND command sequencer configuration register 1
| CMD2EN | Command cycle 2 Enable 0 (B_0x0): Command cycle 2 not issued. 1 (B_0x1): Command cycle 2 (programmed CMD2[7:0]) sent by the command sequencer to the NAND Flash memory after the address cycles. |
| DMADEN | Command sequencer DMA request data enable 0 (B_0x0): No DMA request transfer 1 (B_0x1): A DMA request transfer |
| ACYNBR | Address Cycle number 0 (B_0x0): No address cycle. 1 (B_0x1): 1 address cycle 2 (B_0x2): 2 address cycles 3 (B_0x3): 3 address cycles 4 (B_0x4): 4 address cycles 5 (B_0x5): 5 address cycles |
| CMD1 | Command 1 sequencer |
| CMD2 | Command 2 sequencer |
| CMD1T | Command 1 Sequencer timings 0 (B_0x0): CMD1 issued with the timings programmed in FMC_PMEM 1 (B_0x1): CMD1 issued with the timings programmed in FMC_PATT |
| CMD2T | Command 2 Sequencer timings 0 (B_0x0): CMD2 issued with the timings programmed in FMC_PMEM 1 (B_0x1): CMD2 issued with the timings programmed in FMC_PATT |