TCLR=B_0x0, PBKEN=B_0x0, PWID=B_0x0, ECCSS=B_0x0, PWAITEN=B_0x0, ECCEN=B_0x0, WEN=B_0x0, BCHECC=B_0x0, ECCALG=B_0x0, TAR=B_0x0
NAND Flash programmable control register
| PWAITEN | Wait feature enable bit 0 (B_0x0): disabled (default) 1 (B_0x1): enabled |
| PBKEN | NAND Flash memory region enable bit 0 (B_0x0): Corresponding memory region is disabled (default after reset) 1 (B_0x1): Corresponding memory region is enabled. |
| PWID | Data bus width 0 (B_0x0): 8 bits (default after reset). 1 (B_0x1): 16 bits |
| ECCEN | ECC computation logic enable bit 0 (B_0x0): ECC logic is disabled and reset (default after reset), 1 (B_0x1): ECC logic is enabled. |
| ECCALG | ECC algorithm 0 (B_0x0): Hamming code is selected (default). 1 (B_0x1): BCH code is selected. |
| TCLR | CLE to RE delay. 0 (B_0x0): 1 * fmc_ker_ck cycle 15 (B_0xF): 16 * fmc_ker_ck cycles (default) |
| TAR | ALE to RE delay. 0 (B_0x0): 1 * fmc_ker_ck cycle 15 (B_0xF): 16 * fmc_ker_ck cycles (default) |
| ECCSS | ECC sector size (used to access spare area) 0 (B_0x0): 256 bytes 1 (B_0x1): 512 bytes 2 (B_0x2): 1024 bytes 3 (B_0x3): 2048 bytes (default) 4 (B_0x4): 4096 bytes |
| BCHECC | BCH error correction capability 0 (B_0x0): 4-bit BCH (4-bit error correction and 8-bit error detection per 512 bytes) 1 (B_0x1): 8-bit BCH (8-bit error correction and 16-bit error detection per 512 bytes) |
| WEN | Write enable 0 (B_0x0): Read access enabled 1 (B_0x1): Write access enabled |