stm32 /stm32n6 /STM32N655 /HPDMA /HPDMA_C0LLR

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Interpret as HPDMA_C0LLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LA0 (B_0x0)ULL 0 (B_0x0)UDA 0 (B_0x0)USA 0 (B_0x0)UB1 0 (B_0x0)UT2 0 (B_0x0)UT1

UT2=B_0x0, UDA=B_0x0, USA=B_0x0, UB1=B_0x0, ULL=B_0x0, UT1=B_0x0

Description

HPDMA channel 0 linked-list address register

Fields

LA

pointer (16-bit low-significant address) to the next linked-list data structure

ULL

Update HPDMA_CxLLR register from memory

0 (B_0x0): no HPDMA_CxLLR update

1 (B_0x1): HPDMA_CxLLR update

UDA

Update HPDMA_CxDAR register from memory

0 (B_0x0): no HPDMA_CxDAR update

1 (B_0x1): HPDMA_CxDAR update

USA

update HPDMA_CxSAR from memory

0 (B_0x0): no HPDMA_CxSAR update

1 (B_0x1): HPDMA_CxSAR update

UB1

Update HPDMA_CxBR1 from memory

0 (B_0x0): no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

1 (B_0x1): HPDMA_CxBR1 update

UT2

Update HPDMA_CxTR2 from memory

0 (B_0x0): no HPDMA_CxTR2 update

1 (B_0x1): HPDMA_CxTR2 update

UT1

Update HPDMA_CxTR1 from memory

0 (B_0x0): no HPDMA_CxTR1 update

1 (B_0x1): HPDMA_CxTR1 update

Links

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