stm32 /stm32n6 /STM32N655 /HPDMA /HPDMA_C7TR1

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Interpret as HPDMA_C7TR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SDW_LOG2 0 (B_0x0)SINC 0SBL_10 (B_0x0_PAM_1)PAM0 (B_0x0)SBX 0 (B_0x0)SAP 0 (B_0x0)SSEC 0 (B_0x0)DDW_LOG2 0 (B_0x0)DINC 0DBL_10 (B_0x0)DBX 0 (B_0x0)DHX 0 (B_0x0)DWX 0 (B_0x0)DAP 0 (B_0x0)DSEC

DHX=B_0x0, DBX=B_0x0, DDW_LOG2=B_0x0, DINC=B_0x0, PAM=B_0x0_PAM_1, DWX=B_0x0, SBX=B_0x0, SSEC=B_0x0, DAP=B_0x0, DSEC=B_0x0, SAP=B_0x0, SINC=B_0x0, SDW_LOG2=B_0x0

Description

HPDMA channel 7 transfer register 1

Fields

SDW_LOG2

binary logarithm of the source data width of a burst in bytes

0 (B_0x0): byte

1 (B_0x1): half-word (2 bytes)

2 (B_0x2): word (4 bytes)

3 (B_0x3): If SAP = 0 (AXI), double-word (8 bytes)

SINC

source incrementing burst

0 (B_0x0): fixed burst

1 (B_0x1): contiguously incremented burst

SBL_1

source burst length minus 1, between 0 and 63

PAM

padding/alignment mode

0 (B_0x0_PAM_1): source data is transferred as right aligned, padded with 0s up to the destination data width

1 (B_0x1_PAM_1): source data is transferred as right aligned, sign extended up to the destination data width

2 (B_0x2_PAM_1): successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer

3 (B_0x3_PAM_1): successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer

SBX

source byte exchange within the unaligned half-word of each source word

0 (B_0x0): no byte-based exchange within the unaligned half-word of each source word

1 (B_0x1): the two consecutive bytes within the unaligned half-word of each source word are exchanged.

SAP

source allocated port

0 (B_0x0): port 0 (AXI) allocated

1 (B_0x1): port 1 (AHB) allocated

SSEC

security attribute of the HPDMA transfer from the source

0 (B_0x0): HPDMA transfer non-secure

1 (B_0x1): HPDMA transfer secure

DDW_LOG2

binary logarithm of the destination data width of a burst, in bytes

0 (B_0x0): byte

1 (B_0x1): half-word (2 bytes)

2 (B_0x2): word (4 bytes)

3 (B_0x3): If DAP = 0 (AXI), double-word (8 bytes)

DINC

destination incrementing burst

0 (B_0x0): fixed burst

1 (B_0x1): contiguously incremented burst

DBL_1

destination burst length minus 1, between 0 and 63

DBX

destination byte exchange

0 (B_0x0): no byte-based exchange within half-word

1 (B_0x1): the two consecutive (post PAM) bytes are exchanged in each destination half-word.

DHX

destination half-word exchange

0 (B_0x0): no half-word-based exchanged within word

1 (B_0x1): the two consecutive (post PAM) half-words are exchanged in each destination word.

DWX

destination word exchange

0 (B_0x0): no word-based exchanged within double-word

1 (B_0x1): the two consecutive (post PAM) words are exchanged in each destination double-word.

DAP

destination allocated port

0 (B_0x0): port 0 (AXI) allocated

1 (B_0x1): port 1 (AHB) allocated

DSEC

security attribute of the HPDMA transfer to the destination

0 (B_0x0): HPDMA transfer non-secure

1 (B_0x1): HPDMA transfer secure

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