LPTIM5_CR

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Interpret as LPTIM5_CR

ENABLE=B_0x0

LPTIM5 control register

ENABLE	LPTIM enable 0 (B_0x0): LPTIM is disabled. Writing ‘0’ to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests). 1 (B_0x1): LPTIM is enabled
SNGSTRT	LPTIM start in Single mode
CNTSTRT	Timer start in Continuous mode
COUNTRST	Counter reset
RSTARE	Reset after read enable

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