Regviz

stm32 /stm32n6 /STM32N655 /LTDC /LTDC_L1C1R

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LTDC_L1C1R

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/LTDC/LTDC_L1C1R#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)YIA 0 (B_0x0)YSPA 0 (B_0x0)YFPA 0 (B_0x0)SCA

YSPA=B_0x0, YFPA=B_0x0, SCA=B_0x0, YIA=B_0x0

Description

LTDC layerx configuration 1 register

Fields

YIA

YCbCr 422 interleaved ability for that layer

0 (B_0x0): interleaved not available

1 (B_0x1): interleaved available
YSPA

YCbCr 420 semi-planar ability for that layer

0 (B_0x0): semi-planar not available

1 (B_0x1): semi-planar available
YFPA

YCbCr 420 full-planar ability for that layer

0 (B_0x0): full planar not available

1 (B_0x1): full planar available
SCA

scaling ability for that layer

0 (B_0x0): scaling not available

1 (B_0x1): scaling available

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32