PROCDIV=B_0x0, CCK1DIR=B_0x0, CKGMOD=B_0x0, CKGDEN=B_0x0, CCKDIV=B_0x0, CCK0DIR=B_0x0, CCK1EN=B_0x0, CCK0EN=B_0x0, TRGSENS=B_0x0, CKGACTIVE=B_0x0
MDF clock generator control register
| CKGDEN | CKGEN dividers enable 0 (B_0x0): CKGEN dividers disabled 1 (B_0x1): CKGEN dividers enabled |
| CCK0EN | MDF_CCK0 clock enable 0 (B_0x0): Bitstream clock not generated 1 (B_0x1): Bitstream clock generated on the MDF_CCK0 pad |
| CCK1EN | MDF_CCK1 clock enable 0 (B_0x0): Bitstream clock not generated 1 (B_0x1): Bitstream clock generated on the MDF_CCK1 pad |
| CKGMOD | Clock generator mode 0 (B_0x0): The kernel clock is provided to the dividers as soon as CKGDEN is set to 1. 1 (B_0x1): The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met. |
| CCK0DIR | MDF_CCK0 direction 0 (B_0x0): MDF_CCK0 pin direction is in input. 1 (B_0x1): MDF_CCK0 pin direction is in output. |
| CCK1DIR | MDF_CCK1 direction 0 (B_0x0): MDF_CCK1 pin direction is in input. 1 (B_0x1): MDF_CCK1 pin direction is in output. |
| TRGSENS | CKGEN trigger sensitivity selection 0 (B_0x0): A rising edge event triggers the activation of CKGEN dividers. 1 (B_0x1): A falling edge even triggers the activation of CKGEN dividers. |
| TRGSRC | Digital filter trigger signal selection 2 (B_0x2): mdf_trg[0] selected 3 (B_0x3): mdf_trg[1] selected 15 (B_0xF): mdf_trg[13] selected |
| CCKDIV | Divider to control the MDF_CCK clock 0 (B_0x0): The MDF_CCK clock is mdf_proc_ck. 1 (B_0x1): The MDF_CCK clock is mdf_proc_ck / 2. 2 (B_0x2): The MDF_CCK clock is mdf_proc_ck / 3. 15 (B_0xF): The MDF_CCK clock is mdf_proc_ck / 16. |
| PROCDIV | Divider to control the serial interface clock 0 (B_0x0): mdf_ker_ck provided to the SITF 1 (B_0x1): mdf_ker_ck/2 provided to the SITF |
| CKGACTIVE | Clock generator active flag 0 (B_0x0): The clock generator is not active and can be configured if needed. 1 (B_0x1): The clock generator is active and protected fields cannot be configured. |