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stm32 /stm32n6 /STM32N655 /PWR /PWR_BDCR1

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Interpret as PWR_BDCR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)MONEN 0 (B_0x0)VBATL 0 (B_0x0)VBATH 0 (B_0x0)TEMPL 0 (B_0x0)TEMPH

VBATL=B_0x0, TEMPL=B_0x0, MONEN=B_0x0, TEMPH=B_0x0, VBATH=B_0x0

Description

PWR backup domain control register 1

Fields

MONEN

Vless thansub>BATless than/sub> and temperature monitoring enable

0 (B_0x0): Vless thansub>BATless than/sub> and temperature monitoring disabled

1 (B_0x1): Vless thansub>BATless than/sub> and temperature monitoring enabled
VBATL

Vless thansub>BATless than/sub> level monitoring versus low threshold

0 (B_0x0): Vless thansub>BATless than/sub> level above low threshold level

1 (B_0x1): Vless thansub>BATless than/sub> level equal or below low threshold level
VBATH

Vless thansub>BATless than/sub> level monitoring versus high threshold

0 (B_0x0): Vless thansub>BATless than/sub> level below high threshold level.

1 (B_0x1): Vless thansub>BATless than/sub> level equal or above high threshold level
TEMPL

Temperature level monitoring versus low threshold

0 (B_0x0): Temperature above low threshold level

1 (B_0x1): Temperature equal or below low threshold level
TEMPH

Temperature level monitoring versus high threshold

0 (B_0x0): Temperature below high threshold level

1 (B_0x1): Temperature equal or above high threshold level

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32