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stm32 /stm32n6 /STM32N655 /PWR /PWR_CR4

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Interpret as PWR_CR4

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TCMRBSEN 0 (B_0x0)TCMFLXRBSEN

TCMRBSEN=B_0x0, TCMFLXRBSEN=B_0x0

Description

PWR control register 4

Fields

TCMRBSEN

I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode)

0 (B_0x0): I-TCM and D-TCM RAMs backup supply disabled

1 (B_0x1): I-TCM and D-TCM RAMs backup supply enabled in Standby mode
TCMFLXRBSEN

I-TCM FLEXMEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode)

0 (B_0x0): I-TCM FLEXMEM backup supply disabled

1 (B_0x1): I-TCM FLEXMEM backup supply enabled in Standby mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32