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stm32 /stm32n6 /STM32N655 /RCC /RCC_AHB2LPENR

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Interpret as RCC_AHB2LPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RAMCFGLPEN 0 (B_0x0)MDF1LPEN 0 (B_0x0)ADF1LPEN

MDF1LPEN=B_0x0, ADF1LPEN=B_0x0, RAMCFGLPEN=B_0x0

Description

RCC AHB2 Sleep enable register

Fields

RAMCFGLPEN

RAMCFG sleep enable

0 (B_0x0): RAMCFG is disabled in Sleep mode (default after reset)

1 (B_0x1): RAMCFG is enabled in Sleep mode
MDF1LPEN

MDF1 sleep enable

0 (B_0x0): MDF1 is disabled in Sleep mode (default after reset)

1 (B_0x1): MDF1 is enabled in Sleep mode
ADF1LPEN

ADF1 sleep enable

0 (B_0x0): ADF1 is disabled in Sleep mode (default after reset)

1 (B_0x1): ADF1 is enabled in Sleep mode

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32