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stm32 /stm32n6 /STM32N655 /RCC /RCC_AHB5LPENR

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Interpret as RCC_AHB5LPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HPDMA1LPEN 0 (B_0x0)DMA2DLPEN 0 (B_0x0)JPEGLPEN 0 (B_0x0)FMCLPEN 0 (B_0x0)XSPI1LPEN 0 (B_0x0)PSSILPEN 0 (B_0x0)SDMMC2LPEN 0 (B_0x0)SDMMC1LPEN 0 (B_0x0)XSPI2LPEN 0 (B_0x0)XSPIMLPEN 0 (B_0x0)MCE1LPEN 0 (B_0x0)MCE2LPEN 0 (B_0x0)MCE3LPEN 0 (B_0x0)XSPI3LPEN 0 (B_0x0)MCE4LPEN 0 (B_0x0)GFXMMULPEN 0 (B_0x0)GPULPEN 0 (B_0x0)ETH1MACLPEN 0 (B_0x0)ETH1TXLPEN 0 (B_0x0)ETH1RXLPEN 0 (B_0x0)ETH1LPEN 0 (B_0x0)OTG1LPEN 0 (B_0x0)OTGPHY1LPEN 0 (B_0x0)OTGPHY2LPEN 0 (B_0x0)OTG2LPEN 0 (B_0x0)NPUCACHELPEN 0 (B_0x0)NPULPEN

SDMMC1LPEN=B_0x0, FMCLPEN=B_0x0, OTG2LPEN=B_0x0, MCE4LPEN=B_0x0, XSPI1LPEN=B_0x0, PSSILPEN=B_0x0, NPUCACHELPEN=B_0x0, XSPI2LPEN=B_0x0, XSPI3LPEN=B_0x0, ETH1LPEN=B_0x0, DMA2DLPEN=B_0x0, ETH1RXLPEN=B_0x0, MCE2LPEN=B_0x0, JPEGLPEN=B_0x0, HPDMA1LPEN=B_0x0, ETH1MACLPEN=B_0x0, ETH1TXLPEN=B_0x0, GFXMMULPEN=B_0x0, GPULPEN=B_0x0, NPULPEN=B_0x0, OTGPHY1LPEN=B_0x0, MCE3LPEN=B_0x0, XSPIMLPEN=B_0x0, OTG1LPEN=B_0x0, MCE1LPEN=B_0x0, SDMMC2LPEN=B_0x0, OTGPHY2LPEN=B_0x0

Description

RCC AHB5 Sleep enable register

Fields

HPDMA1LPEN

HPDMA1 sleep enable

0 (B_0x0): HPDMA1 is disabled in Sleep mode (default after reset)

1 (B_0x1): HPDMA1 is enabled in Sleep mode
DMA2DLPEN

DMA2D sleep enable

0 (B_0x0): DMA2D is disabled in Sleep mode (default after reset)

1 (B_0x1): DMA2D is enabled in Sleep mode
JPEGLPEN

JPEG sleep enable

0 (B_0x0): JPEG is disabled in Sleep mode (default after reset)

1 (B_0x1): JPEG is enabled in Sleep mode
FMCLPEN

FMC sleep enable

0 (B_0x0): FMC is disabled in Sleep mode (default after reset)

1 (B_0x1): FMC is enabled in Sleep mode
XSPI1LPEN

XSPI1 sleep enable

0 (B_0x0): XSPI1 is disabled in Sleep mode (default after reset)

1 (B_0x1): XSPI1 is enabled in Sleep mode
PSSILPEN

PSSI sleep enable

0 (B_0x0): PSSI is disabled in Sleep mode (default after reset)

1 (B_0x1): PSSI is enabled in Sleep mode
SDMMC2LPEN

SDMMC2 sleep enable

0 (B_0x0): SDMMC2 is disabled in Sleep mode (default after reset)

1 (B_0x1): SDMMC2 is enabled in Sleep mode
SDMMC1LPEN

SDMMC1 sleep enable

0 (B_0x0): SDMMC1 is disabled in Sleep mode (default after reset)

1 (B_0x1): SDMMC1 is enabled in Sleep mode
XSPI2LPEN

XSPI2 sleep enable

0 (B_0x0): XSPI2 is disabled in Sleep mode (default after reset)

1 (B_0x1): XSPI2 is enabled in Sleep mode
XSPIMLPEN

XSPIM sleep enable

0 (B_0x0): XSPIM is disabled in Sleep mode (default after reset)

1 (B_0x1): XSPIM is enabled in Sleep mode
MCE1LPEN

MCE1 sleep enable

0 (B_0x0): MCE1 is disabled in Sleep mode (default after reset)

1 (B_0x1): MCE1 is enabled in Sleep mode
MCE2LPEN

MCE2 sleep enable

0 (B_0x0): MCE2 is disabled in Sleep mode (default after reset)

1 (B_0x1): MCE2 is enabled in Sleep mode
MCE3LPEN

MCE3 sleep enable

0 (B_0x0): MCE3 is disabled in Sleep mode (default after reset)

1 (B_0x1): MCE3 is enabled in Sleep mode
XSPI3LPEN

XSPI3 sleep enable

0 (B_0x0): XSPI3 is disabled in Sleep mode (default after reset)

1 (B_0x1): XSPI3 is enabled in Sleep mode
MCE4LPEN

MCE4 sleep enable

0 (B_0x0): MCE4 is disabled in Sleep mode (default after reset)

1 (B_0x1): MCE4 is enabled in Sleep mode
GFXMMULPEN

GFXMMU sleep enable

0 (B_0x0): GFXMMU is disabled in Sleep mode (default after reset)

1 (B_0x1): GFXMMU is enabled in Sleep mode
GPULPEN

GPU sleep enable

0 (B_0x0): GPU is disabled in Sleep mode (default after reset)

1 (B_0x1): GPU is enabled in Sleep mode
ETH1MACLPEN

ETH1MAC sleep enable

0 (B_0x0): ETH1MAC is disabled in Sleep mode (default after reset)

1 (B_0x1): ETH1MAC is enabled in Sleep mode
ETH1TXLPEN

ETH1TX sleep enable

0 (B_0x0): ETH1TX is disabled in Sleep mode (default after reset)

1 (B_0x1): ETH1TX is enabled in Sleep mode
ETH1RXLPEN

ETH1RX sleep enable

0 (B_0x0): ETH1RX is disabled in Sleep mode (default after reset)

1 (B_0x1): ETH1RX is enabled in Sleep mode
ETH1LPEN

ETH1 sleep enable

0 (B_0x0): ETH1 is disabled in Sleep mode (default after reset)

1 (B_0x1): ETH1 is enabled in Sleep mode
OTG1LPEN

OTG1 sleep enable

0 (B_0x0): OTG1 is disabled in Sleep mode (default after reset)

1 (B_0x1): OTG1 is enabled in Sleep mode
OTGPHY1LPEN

OTGPHY1 sleep enable

0 (B_0x0): OTGPHY1 is disabled in Sleep mode (default after reset)

1 (B_0x1): OTGPHY1 is enabled in Sleep mode
OTGPHY2LPEN

OTGPHY2 sleep enable

0 (B_0x0): OTGPHY2 is disabled in Sleep mode (default after reset)

1 (B_0x1): OTGPHY2 is enabled in Sleep mode
OTG2LPEN

OTG2 sleep enable

0 (B_0x0): OTG2 is disabled in Sleep mode (default after reset)

1 (B_0x1): OTG2 is enabled in Sleep mode
NPUCACHELPEN

NPUCACHE sleep enable

0 (B_0x0): NPUCACHE is disabled in Sleep mode (default after reset)

1 (B_0x1): NPUCACHE is enabled in Sleep mode
NPULPEN

NPU sleep enable

0 (B_0x0): NPU is disabled in Sleep mode (default after reset)

1 (B_0x1): NPU is enabled in Sleep mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32