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stm32 /stm32n6 /STM32N655 /RCC /RCC_APB1LENR

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Interpret as RCC_APB1LENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM2EN 0 (B_0x0)TIM3EN 0 (B_0x0)TIM4EN 0 (B_0x0)TIM5EN 0 (B_0x0)TIM6EN 0 (B_0x0)TIM7EN 0 (B_0x0)TIM12EN 0 (B_0x0)TIM13EN 0 (B_0x0)TIM14EN 0 (B_0x0)LPTIM1EN 0 (B_0x0)WWDGEN 0 (B_0x0)TIM10EN 0 (B_0x0)TIM11EN 0 (B_0x0)SPI2EN 0 (B_0x0)SPI3EN 0 (B_0x0)SPDIFRX1EN 0 (B_0x0)USART2EN 0 (B_0x0)USART3EN 0 (B_0x0)UART4EN 0 (B_0x0)UART5EN 0 (B_0x0)I2C1EN 0 (B_0x0)I2C2EN 0 (B_0x0)I2C3EN 0 (B_0x0)I3C1EN 0 (B_0x0)I3C2EN 0 (B_0x0)UART7EN 0 (B_0x0)UART8EN

I2C2EN=B_0x0, I2C1EN=B_0x0, UART8EN=B_0x0, WWDGEN=B_0x0, LPTIM1EN=B_0x0, TIM7EN=B_0x0, TIM14EN=B_0x0, TIM5EN=B_0x0, TIM10EN=B_0x0, UART4EN=B_0x0, TIM6EN=B_0x0, I2C3EN=B_0x0, TIM4EN=B_0x0, TIM3EN=B_0x0, SPI3EN=B_0x0, UART5EN=B_0x0, TIM2EN=B_0x0, USART2EN=B_0x0, SPI2EN=B_0x0, UART7EN=B_0x0, USART3EN=B_0x0, TIM13EN=B_0x0, TIM12EN=B_0x0, SPDIFRX1EN=B_0x0, I3C2EN=B_0x0, TIM11EN=B_0x0, I3C1EN=B_0x0

Description

RCC APB1L enable register

Fields

TIM2EN

TIM2 enable

0 (B_0x0): TIM2 is disabled (default after reset)

1 (B_0x1): TIM2 is enabled
TIM3EN

TIM3 enable

0 (B_0x0): TIM3 is disabled (default after reset)

1 (B_0x1): TIM3 is enabled
TIM4EN

TIM4 enable

0 (B_0x0): TIM4 is disabled (default after reset)

1 (B_0x1): TIM4 is enabled
TIM5EN

TIM5 enable

0 (B_0x0): TIM5 is disabled (default after reset)

1 (B_0x1): TIM5 is enabled
TIM6EN

TIM6 enable

0 (B_0x0): TIM6 is disabled (default after reset)

1 (B_0x1): TIM6 is enabled
TIM7EN

TIM7 enable

0 (B_0x0): TIM7 is disabled (default after reset)

1 (B_0x1): TIM7 is enabled
TIM12EN

TIM12 enable

0 (B_0x0): TIM12 is disabled (default after reset)

1 (B_0x1): TIM12 is enabled
TIM13EN

TIM13 enable

0 (B_0x0): TIM13 is disabled (default after reset)

1 (B_0x1): TIM13 is enabled
TIM14EN

TIM14 enable

0 (B_0x0): TIM14 is disabled (default after reset)

1 (B_0x1): TIM14 is enabled
LPTIM1EN

LPTIM1 enable

0 (B_0x0): LPTIM1 is disabled (default after reset)

1 (B_0x1): LPTIM1 is enabled
WWDGEN

WWDG enable

0 (B_0x0): WWDG is disabled (default after reset)

1 (B_0x1): WWDG is enabled
TIM10EN

TIM10 enable

0 (B_0x0): TIM10 is disabled (default after reset)

1 (B_0x1): TIM10 is enabled
TIM11EN

TIM11 enable

0 (B_0x0): TIM11 is disabled (default after reset)

1 (B_0x1): TIM11 is enabled
SPI2EN

SPI2 enable

0 (B_0x0): SPI2 is disabled (default after reset)

1 (B_0x1): SPI2 is enabled
SPI3EN

SPI3 enable

0 (B_0x0): SPI3 is disabled (default after reset)

1 (B_0x1): SPI3 is enabled
SPDIFRX1EN

SPDIFRX1 enable

0 (B_0x0): SPDIFRX1 is disabled (default after reset)

1 (B_0x1): SPDIFRX1 is enabled
USART2EN

USART2 enable

0 (B_0x0): USART2 is disabled (default after reset)

1 (B_0x1): USART2 is enabled
USART3EN

USART3 enable

0 (B_0x0): USART3 is disabled (default after reset)

1 (B_0x1): USART3 is enabled
UART4EN

UART4 enable

0 (B_0x0): UART4 is disabled (default after reset)

1 (B_0x1): UART4 is enabled
UART5EN

UART5 enable

0 (B_0x0): UART5 is disabled (default after reset)

1 (B_0x1): UART5 is enabled
I2C1EN

I2C1 enable

0 (B_0x0): I2C1 is disabled (default after reset)

1 (B_0x1): I2C1 is enabled
I2C2EN

I2C2 enable

0 (B_0x0): I2C2 is disabled (default after reset)

1 (B_0x1): I2C2 is enabled
I2C3EN

I2C3 enable

0 (B_0x0): I2C3 is disabled (default after reset)

1 (B_0x1): I2C3 is enabled
I3C1EN

I3C1 enable

0 (B_0x0): I3C1 is disabled (default after reset)

1 (B_0x1): I3C1 is enabled
I3C2EN

I3C2 enable

0 (B_0x0): I3C2 is disabled (default after reset)

1 (B_0x1): I3C2 is enabled
UART7EN

UART7 enable

0 (B_0x0): UART7 is disabled (default after reset)

1 (B_0x1): UART7 is enabled
UART8EN

UART8 enable

0 (B_0x0): UART8 is disabled (default after reset)

1 (B_0x1): UART8 is enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32