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stm32 /stm32n6 /STM32N655 /RCC /RCC_APB3ENR

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Interpret as RCC_APB3ENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DFTEN

DFTEN=B_0x0

Description

RCC APB3 enable register

Fields

DFTEN

DFT enable

0 (B_0x0): DFT is disabled (default after reset)

1 (B_0x1): DFT is enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32