stm32 /stm32n6 /STM32N655 /RCC /RCC_APB4LENR

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Interpret as RCC_APB4LENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HDPEN 0 (B_0x0)LPUART1EN 0 (B_0x0)SPI6EN 0 (B_0x0)I2C4EN 0 (B_0x0)LPTIM2EN 0 (B_0x0)LPTIM3EN 0 (B_0x0)LPTIM4EN 0 (B_0x0)LPTIM5EN 0 (B_0x0)VREFBUFEN 0 (B_0x0)RTCEN 0 (B_0x0)RTCAPBEN 0 (B_0x0)R2GRETEN 0 (B_0x0)R2GNPUEN 0 (B_0x0)SERFEN

SERFEN=B_0x0, LPTIM2EN=B_0x0, VREFBUFEN=B_0x0, I2C4EN=B_0x0, R2GRETEN=B_0x0, SPI6EN=B_0x0, LPTIM3EN=B_0x0, LPUART1EN=B_0x0, LPTIM4EN=B_0x0, RTCAPBEN=B_0x0, HDPEN=B_0x0, R2GNPUEN=B_0x0, LPTIM5EN=B_0x0, RTCEN=B_0x0

Description

RCC APB4L enable register

Fields

HDPEN

HDP enable

0 (B_0x0): HDP is disabled (default after reset)

1 (B_0x1): HDP is enabled

LPUART1EN

LPUART1 enable

0 (B_0x0): LPUART1 is disabled (default after reset)

1 (B_0x1): LPUART1 is enabled

SPI6EN

SPI6 enable

0 (B_0x0): SPI6 is disabled (default after reset)

1 (B_0x1): SPI6 is enabled

I2C4EN

I2C4 enable

0 (B_0x0): I2C4 is disabled (default after reset)

1 (B_0x1): I2C4 is enabled

LPTIM2EN

LPTIM2 enable

0 (B_0x0): LPTIM2 is disabled (default after reset)

1 (B_0x1): LPTIM2 is enabled

LPTIM3EN

LPTIM3 enable

0 (B_0x0): LPTIM3 is disabled (default after reset)

1 (B_0x1): LPTIM3 is enabled

LPTIM4EN

LPTIM4 enable

0 (B_0x0): LPTIM4 is disabled (default after reset)

1 (B_0x1): LPTIM4 is enabled

LPTIM5EN

LPTIM5 enable

0 (B_0x0): LPTIM5 is disabled (default after reset)

1 (B_0x1): LPTIM5 is enabled

VREFBUFEN

VREFBUF enable

0 (B_0x0): VREFBUF is disabled (default after reset)

1 (B_0x1): VREFBUF is enabled

RTCEN

RTC enable

0 (B_0x0): RTC is disabled (default after reset)

1 (B_0x1): RTC is enabled

RTCAPBEN

RTCAPB enable

0 (B_0x0): RTCAPB is disabled (default after reset)

1 (B_0x1): RTCAPB is enabled

R2GRETEN

R2GRET enable

0 (B_0x0): R2GRET is disabled (default after reset)

1 (B_0x1): R2GRET is enabled

R2GNPUEN

R2GNPU enable

0 (B_0x0): R2GNPU is disabled (default after reset)

1 (B_0x1): R2GNPU is enabled

SERFEN

SERF enable

0 (B_0x0): SERF is disabled (default after reset)

1 (B_0x1): SERF is enabled

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