ADF1SEL=B_0x0, DCMIPPSEL=B_0x0, ADCPRE=B_0x0, ADC12SEL=B_0x0
RCC clock configuration for independent peripheral register1
| ADF1SEL | Source selection for the ADF1 kernel clock 0 (B_0x0): hclk2 selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic7_ck selected as reference clock 3 (B_0x3): ic8_ck selected as reference clock 4 (B_0x4): msi_ck selected as reference clock 5 (B_0x5): hsi_div_ck selected as reference clock 6 (B_0x6): I2S_CKIN selected as reference clock 7 (B_0x7): timg_ck selected as reference clock |
| ADC12SEL | Source selection for the ADC12 kernel clock 0 (B_0x0): hclk1 selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic7_ck selected as reference clock 3 (B_0x3): ic8_ck selected as reference clock 4 (B_0x4): msi_ck selected as reference clock 5 (B_0x5): hsi_div_ck selected as reference clock 6 (B_0x6): I2S_CKIN selected as reference clock 7 (B_0x7): timg_ck selected as reference clock |
| ADCPRE | ADC12 Prog clock divider selection (for clock ck_icn_p_adf1) 0 (B_0x0): ck_icn_p_adf1 is divided by 1 1 (B_0x1): ck_icn_p_adf1 is divided by 2 2 (B_0x2): ck_icn_p_adf1 is divided by 3 3 (B_0x3): ck_icn_p_adf1 is divided by 4 |
| DCMIPPSEL | Source selection for the DCMIPP kernel clock 0 (B_0x0): pclk5 selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic17_ck selected as reference clock 3 (B_0x3): hsi_div_ck selected as reference clock |