FDCANSEL=B_0x0, DFTSEL=B_0x0, FMCSEL=B_0x0
RCC clock configuration for independent peripheral register3
| FDCANSEL | Source selection for the FDCAN kernel clock 0 (B_0x0): pclk1 selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic19_ck selected as reference clock 3 (B_0x3): hse_ck selected as reference clock |
| FMCSEL | Source selection for the FMC kernel clock 0 (B_0x0): hclk5 selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic3_ck selected as reference clock 3 (B_0x3): ic4_ck selected as reference clock |
| DFTSEL | Source selection for the DFT kernel clock 0 (B_0x0): jtag_tck selected as reference clock (default after reset) 1 (B_0x1): pclk3 selected as reference clock |