MDF1SEL=B_0x0, MCO2SEL=B_0x0, MCO2PRE=B_0x0, MCO1PRE=B_0x0, MCO1SEL=B_0x0
RCC lock configuration for independent peripheral register5
| MCO1SEL | Source selection for the MCO1 kernel clock 0 (B_0x0): hsi_div_ck selected as reference clock (default after reset) 1 (B_0x1): lse_ck selected as reference clock 2 (B_0x2): msi_ck selected as reference clock 3 (B_0x3): lsi_ck selected as reference clock 4 (B_0x4): hse_ck selected as reference clock 5 (B_0x5): ic5_ck selected as reference clock 6 (B_0x6): ic10_ck selected as reference clock 7 (B_0x7): sysa_ck selected as reference clock |
| MCO1PRE | MCO1 Prog clock divider selection (for clock ck_icn_p_mce3) 0 (B_0x0): ck_icn_p_mce3 is divided by 1 1 (B_0x1): ck_icn_p_mce3 is divided by 2 2 (B_0x2): ck_icn_p_mce3 is divided by 3 3 (B_0x3): ck_icn_p_mce3 is divided by 4 15 (B_0xF): ck_icn_p_mce3 is divided by 16 |
| MCO2SEL | Source selection for the MCO2 kernel clock 0 (B_0x0): hsi_div_ck selected as reference clock (default after reset) 1 (B_0x1): lse_ck selected as reference clock 2 (B_0x2): msi_ck selected as reference clock 3 (B_0x3): lsi_ck selected as reference clock 4 (B_0x4): hse_ck selected as reference clock 5 (B_0x5): ic15_ck selected as reference clock 6 (B_0x6): ic20_ck selected as reference clock 7 (B_0x7): sysb_ck selected as reference clock |
| MCO2PRE | MCO2 Prog clock divider selection (for clock ck_icn_p_mce4) 0 (B_0x0): ck_icn_p_mce4 is divided by 1 1 (B_0x1): ck_icn_p_mce4 is divided by 2 2 (B_0x2): ck_icn_p_mce4 is divided by 3 3 (B_0x3): ck_icn_p_mce4 is divided by 4 15 (B_0xF): ck_icn_p_mce4 is divided by 16 |
| MDF1SEL | Source selection for the MDF1 kernel clock 0 (B_0x0): hclk2 selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic7_ck selected as reference clock 3 (B_0x3): ic8_ck selected as reference clock 4 (B_0x4): msi_ck selected as reference clock 5 (B_0x5): hsi_div_ck selected as reference clock 6 (B_0x6): I2S_CKIN selected as reference clock 7 (B_0x7): timg_ck selected as reference clock |