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stm32 /stm32n6 /STM32N655 /RCC /RCC_DIVENSR

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Interpret as RCC_DIVENSR

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https://regviz.com/r/stm32/stm32n6/STM32N645/RCC/RCC_DIVENSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IC1ENS)IC1ENS 0 (IC2ENS)IC2ENS 0 (IC3ENS)IC3ENS 0 (IC4ENS)IC4ENS 0 (IC5ENS)IC5ENS 0 (IC6ENS)IC6ENS 0 (IC7ENS)IC7ENS 0 (IC8ENS)IC8ENS 0 (IC9ENS)IC9ENS 0 (IC10ENS)IC10ENS 0 (IC11ENS)IC11ENS 0 (IC12ENS)IC12ENS 0 (IC13ENS)IC13ENS 0 (IC14ENS)IC14ENS 0 (IC15ENS)IC15ENS 0 (IC16ENS)IC16ENS 0 (IC17ENS)IC17ENS 0 (IC18ENS)IC18ENS 0 (IC19ENS)IC19ENS 0 (IC20ENS)IC20ENS

Description

RCC Divider enable register

Fields

IC1ENS

IC1 enable
IC2ENS

IC2 enable
IC3ENS

IC3 enable
IC4ENS

IC4 enable
IC5ENS

IC5 enable
IC6ENS

IC6 enable
IC7ENS

IC7 enable
IC8ENS

IC8 enable
IC9ENS

IC9 enable
IC10ENS

IC10 enable
IC11ENS

IC11 enable
IC12ENS

IC12 enable
IC13ENS

IC13 enable
IC14ENS

IC14 enable
IC15ENS

IC15 enable
IC16ENS

IC16 enable
IC17ENS

IC17 enable
IC18ENS

IC18 enable
IC19ENS

IC19 enable
IC20ENS

IC20 enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32