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stm32 /stm32n6 /STM32N655 /RCC /RCC_IC1CFGR

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Interpret as RCC_IC1CFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IC1INT0 (B_0x0)IC1SEL

IC1INT=B_0x0, IC1SEL=B_0x0

Description

RCC IC1 configuration register

Fields

IC1INT

Divider IC1 integer division factor

0 (B_0x0): IC1 = pllx_ck

1 (B_0x1): IC1 = pllx_ck / 2

2 (B_0x2): IC1 = pllx_ck / 3 (default after reset)

3 (B_0x3): IC1 = pllx_ck / 4

255 (B_0xFF): IC1 = pllx_ck / 256
IC1SEL

Divider IC1 Source Selection

0 (B_0x0): pll1_ck is selected (default after reset)

1 (B_0x1): pll2_ck is selected

2 (B_0x2): hsi_ck = hsi_osc_ck / 4

3 (B_0x3): hsi_ck = hsi_osc_ck / 8

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32