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stm32 /stm32n6 /STM32N655 /RCC /RCC_MISCENR

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Interpret as RCC_MISCENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBGEN 0 (B_0x0)MCO1EN 0 (B_0x0)MCO2EN 0 (B_0x0)XSPIPHYCOMPEN 0 (B_0x0)PEREN

XSPIPHYCOMPEN=B_0x0, PEREN=B_0x0, DBGEN=B_0x0, MCO2EN=B_0x0, MCO1EN=B_0x0

Description

RCC miscellaneous configuration enable register

Fields

DBGEN

DBG enable

0 (B_0x0): DBG is disabled (default after reset)

1 (B_0x1): DBG is enabled
MCO1EN

MCO1 enable

0 (B_0x0): MCO1 is disabled (default after reset)

1 (B_0x1): MCO1 is enabled
MCO2EN

MCO2 enable

0 (B_0x0): MCO2 is disabled (default after reset)

1 (B_0x1): MCO2 is enabled
XSPIPHYCOMPEN

XSPIPHYCOMP enable

0 (B_0x0): XSPIPHYCOMP is disabled (default after reset)

1 (B_0x1): XSPIPHYCOMP is enabled
PEREN

PER enable

0 (B_0x0): PER is disabled (default after reset)

1 (B_0x1): PER is enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32