PLL2MODSSDIS=B_0x0, PLL2PDIV2=B_0x0, PLL2MODDSEN=B_0x0, PLL2MODSSRST=B_0x0, PLL2DACEN=B_0x0, PLL2MODSPRDW=B_0x0, PLL2PDIVEN=B_0x0, PLL2PDIV1=B_0x0
RCC PLL2 configuration register 3
| PLL2MODSSRST | PLL2 Modulation Spread Spectrum reset 0 (B_0x0): The PLL2 Modulation Spread Spectrum reset module is released 1 (B_0x1): The PLL2 Modulation Spread Spectrum reset module is asserted (default after reset) |
| PLL2DACEN | PLL2 noise canceling DAC enable in fractional mode. 0 (B_0x0): DAC is not active (default after reset) 1 (B_0x1): DAC is active |
| PLL2MODSSDIS | PLL2 Modulation Spread-Spectrum Disable 0 (B_0x0): Modulation Spread-Spectrum is active (and Fractional Divide inactive) 1 (B_0x1): Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset) |
| PLL2MODDSEN | PLL2 Modulation Spread-Spectrum (and Fractional Divide) enable 0 (B_0x0): Modulation Spread-Spectrum and Fractional Divide are not active (default after reset) 1 (B_0x1): Modulation Spread-Spectrum and Fractional Divide are active |
| PLL2MODSPRDW | PLL2 Modulation Down Spread 0 (B_0x0): Center-spread modulation selected (default after reset) 1 (B_0x1): Down-spread modulation selected |
| PLL2MODDIV | PLL2 Modulation Division frequency adjustment |
| PLL2MODSPR | PLL2 Modulation Spread depth adjustment |
| PLL2PDIV2 | PLL2 VCO frequency divider level 2 0 (B_0x0): Not applicable 1 (B_0x1): VCO output is divided by 1 (minimum value) (default after reset) 7 (B_0x7): VCO output is divided by 7 |
| PLL2PDIV1 | PLL2 VCO frequency divider level 1 0 (B_0x0): Not applicable 1 (B_0x1): VCO output is divided by 1 (minimum value) (default after reset) 7 (B_0x7): VCO output is divided by 7 |
| PLL2PDIVEN | PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable 0 (B_0x0): POSTDIV1 and POSTDIV2 are powered down 1 (B_0x1): POSTDIV1 and POSTDIV2 dividers are active (default after reset) |