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stm32 /stm32n6 /STM32N655 /RCC /RCC_SR

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Interpret as RCC_SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LSIRDY 0 (B_0x0)LSERDY 0 (B_0x0)MSIRDY 0 (B_0x0)HSIRDY 0 (B_0x0)HSERDY 0 (B_0x0)PLL1RDY 0 (B_0x0)PLL2RDY 0 (B_0x0)PLL3RDY 0 (B_0x0)PLL4RDY

PLL2RDY=B_0x0, PLL1RDY=B_0x0, PLL4RDY=B_0x0, HSERDY=B_0x0, PLL3RDY=B_0x0, LSERDY=B_0x0, HSIRDY=B_0x0, LSIRDY=B_0x0, MSIRDY=B_0x0

Description

RCC status register

Fields

LSIRDY

LSI clock ready flag

0 (B_0x0): LSI is not ready (default after reset)

1 (B_0x1): LSI is ready
LSERDY

LSE clock ready flag

0 (B_0x0): LSE is not ready (default after reset)

1 (B_0x1): LSE is ready
MSIRDY

MSI clock ready flag

0 (B_0x0): MSI is not ready (default after reset)

1 (B_0x1): MSI is ready
HSIRDY

HSI clock ready flag

0 (B_0x0): HSI is not ready

1 (B_0x1): HSI is ready (default after reset)
HSERDY

HSE clock ready flag

0 (B_0x0): HSE is not ready (default after reset)

1 (B_0x1): HSE is ready
PLL1RDY

PLL1 clock ready flag

0 (B_0x0): PLL1 unlocked (default after reset)

1 (B_0x1): PLL1 locked
PLL2RDY

PLL2 clock ready flag

0 (B_0x0): PLL2 unlocked (default after reset)

1 (B_0x1): PLL2 locked
PLL3RDY

PLL3 clock ready flag

0 (B_0x0): PLL3 unlocked (default after reset)

1 (B_0x1): PLL3 locked
PLL4RDY

PLL4 clock ready flag

0 (B_0x0): PLL4 unlocked (default after reset)

1 (B_0x1): PLL4 locked

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32