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stm32 /stm32n6 /STM32N655 /RISAF /RISAF_CR

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Interpret as RISAF_CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GLOCK

GLOCK=B_0x0

Description

RISAF configuration register

Fields

GLOCK

global lock

0 (B_0x0): RISAF registers are writable.

1 (B_0x1): All writes to RISAF registers are ignored, except RISAF_IACR, RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR and RISAF_REGx_zENDR (z = A to B).

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32