RNGEN=B_0x0, NISTC=B_0x0, IE=B_0x0, CED=B_0x0, ARDIS=B_0x0, CLKDIV=B_0x0, CONFIGLOCK=B_0x0
RNG control register
| RNGEN | True random number generator enable 0 (B_0x0): True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated. 1 (B_0x1): True random number generator is enabled. |
| IE | Interrupt enable 0 (B_0x0): RNG interrupt is disabled 1 (B_0x1): RNG interrupt is enabled. An interrupt is pending as soon as DRDY = 1, SEIS = 1 or CEIS = 1 in the RNG_SR register. |
| CED | Clock error detection 0 (B_0x0): Clock error detection enabled 1 (B_0x1): Clock error detection is disabled |
| ARDIS | Auto reset disable 0 (B_0x0): When a noise source error occurs RNG performs an automatic reset to clear the SECS bit. 1 (B_0x1): When a noise source error occurs the application must reset RNG by writing CONDRST to 1 then to 0, in order to restart random number generation. |
| RNG_CONFIG3 | RNG configuration 3 |
| NISTC | NIST custom 0 (B_0x0): Hardware default values for NIST compliant RNG. In this configuration per 128-bit output 1 (B_0x1): Custom values for NIST compliant RNG. See Section 47.6: RNG entropy source validation for proposed configuration. |
| RNG_CONFIG2 | RNG configuration 2 |
| CLKDIV | Clock divider factor 0 (B_0x0): internal RNG clock after divider is similar to incoming RNG clock. 1 (B_0x1): two RNG clock cycles per internal RNG clock. 2 (B_0x2): 2less thansup>2less than/sup> (= 4) RNG clock cycles per internal RNG clock. 15 (B_0xF): 2less thansup>15less than/sup> RNG clock cycles per internal clock (for example. an incoming 48 MHz RNG clock becomes a 1.5 kHz internal RNG clock) |
| RNG_CONFIG1 | RNG configuration 1 |
| CONDRST | Conditioning soft reset |
| CONFIGLOCK | RNG Config lock 0 (B_0x0): Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are allowed. 1 (B_0x1): Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next RNG reset. |