Regviz

stm32 /stm32n6 /STM32N655 /RNG /RNG_NSCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RNG_NSCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/RNG/RNG_NSCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0EN_OSC1 0EN_OSC2 0EN_OSC3 0EN_OSC4 0EN_OSC5 0EN_OSC6

Description

RNG noise source control register

Fields

EN_OSC1

Each bit drives one oscillator enable signal input of instance number 1, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.
EN_OSC2

Each bit drives one oscillator enable signal input of instance number 2, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.
EN_OSC3

Each bit drives one oscillator enable signal input of instance number 3, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.
EN_OSC4

Each bit drives one oscillator enable signal input of instance number 4, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.
EN_OSC5

Each bit drives one oscillator enable signal input of instance number 5, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.
EN_OSC6

Each bit drives one oscillator enable signal input of instance number 6, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32