SECS=B_0x0, SEIS=B_0x0, CECS=B_0x0, DRDY=B_0x0, CEIS=B_0x0
RNG status register
| DRDY | Data ready 0 (B_0x0): The RNG_DR register is not yet valid, no random data is available. 1 (B_0x1): The RNG_DR register contains valid random data. |
| CECS | Clock error current status 0 (B_0x0): The RNG clock is correct (fless thansub>RNGCLKless than/sub>> fless thansub>HCLKless than/sub>/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 1 (B_0x1): The RNG clock is too slow (fless thansub>RNGCLKless than/sub>less than fless thansub>HCLKless than/sub>/32). |
| SECS | Seed error current status 0 (B_0x0): No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 1 (B_0x1): At least one of the following faulty sequences has been detected: |
| CEIS | Clock error interrupt status 0 (B_0x0): The RNG clock is correct (fless thansub>RNGCLKless than/sub>> fless thansub>HCLKless than/sub>/32) 1 (B_0x1): The RNG clock before the internal divider is detected too slow (fless thansub>RNGCLKless than/sub>less than fless thansub>HCLKless than/sub>/32) |
| SEIS | Seed error interrupt status 0 (B_0x0): No faulty sequence detected 1 (B_0x1): At least one faulty sequence is detected. See SECS bit description for details. |