LSBFIRST=B_0x0, CKSTR=B_0x0, MCKDIV=B_0x0, PRTCFG=B_0x0, MODE=B_0x0, NODIV=B_0x0, DMAEN=B_0x0, SAIEN=B_0x0, SYNCEN=B_0x0, MCKEN=B_0x0, OSR=B_0x0, OUTDRIV=B_0x0, MONO=B_0x0
SAI configuration register 1
| MODE | SAIx audio block mode 0 (B_0x0): Master transmitter 1 (B_0x1): Master receiver 2 (B_0x2): Slave transmitter 3 (B_0x3): Slave receiver |
| PRTCFG | Protocol configuration 0 (B_0x0): Free protocol. Free protocol enables to use the powerful config uration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP…) by setting most of the configuration register bits as well as frame configuration register. 1 (B_0x1): SPDIF protocol 2 (B_0x2): AC’97 protocol |
| DS | Data size 2 (B_0x2): 8 bits 3 (B_0x3): 10 bits 4 (B_0x4): 16 bits 5 (B_0x5): 20 bits 6 (B_0x6): 24 bits 7 (B_0x7): 32 bits |
| LSBFIRST | Least significant bit first 0 (B_0x0): Data are transferred with MSB first 1 (B_0x1): Data are transferred with LSB first |
| CKSTR | Clock strobing edge 0 (B_0x0): Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge. 1 (B_0x1): Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge. |
| SYNCEN | Synchronization enable 0 (B_0x0): audio subblock in asynchronous mode. 1 (B_0x1): audio subblock is synchronous with the other internal audio subblock. In this case, the audio subblock must be configured in slave mode 2 (B_0x2): audio subblock is synchronous with an external SAI embedded peripheral. In this case the audio subblock should be configured in Slave mode. |
| MONO | Mono mode 0 (B_0x0): Stereo mode 1 (B_0x1): Mono mode. |
| OUTDRIV | Output drive 0 (B_0x0): Audio block output driven when SAIEN is set 1 (B_0x1): Audio block output driven immediately after the setting of this bit. |
| SAIEN | Audio block enable 0 (B_0x0): SAI audio block disabled 1 (B_0x1): SAI audio block enabled. |
| DMAEN | DMA enable 0 (B_0x0): DMA disabled 1 (B_0x1): DMA enabled |
| NODIV | No divider 0 (B_0x0): the ratio between the Master clock generator and frame synchronization is fixed to 256 or 512 1 (B_0x1): the ratio between the Master clock generator and frame synchronization depends on FRL[7:0] |
| MCKDIV | Master clock divider 0 (B_0x0): Divides by 1 the kernel clock input (sai_x_ker_ck). |
| OSR | Oversampling ratio for master clock 0 (B_0x0): Master clock frequency = Fless thansub>FSless than/sub> x 256 1 (B_0x1): Master clock frequency = Fless thansub>FSless than/sub> x 512 |
| MCKEN | Master clock generation enable 0 (B_0x0): The master clock is not generated 1 (B_0x1): The master clock is generated independently of SAIEN bit |