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stm32 /stm32n6 /STM32N655 /SAI1 /SAI_BFRCR

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Interpret as SAI_BFRCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FRL0FSALL0 (B_0x0)FSDEF 0 (B_0x0)FSPOL 0 (B_0x0)FSOFF

FSPOL=B_0x0, FSDEF=B_0x0, FSOFF=B_0x0

Description

SAI frame configuration register

Fields

FRL

Frame length.
FSALL

Frame synchronization active level length.
FSDEF

Frame synchronization definition.

0 (B_0x0): FS signal is a start frame signal

1 (B_0x1): FS signal is a start of frame signal + channel side identification
FSPOL

Frame synchronization polarity.

0 (B_0x0): FS is active low (falling edge)

1 (B_0x1): FS is active high (rising edge)
FSOFF

Frame synchronization offset.

0 (B_0x0): FS is asserted on the first bit of the slot 0.

1 (B_0x1): FS is asserted one bit before the first bit of the slot 0.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32