stm32 /stm32n6 /STM32N655 /SDMMC1 /SDMMC_IDMALAR

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Interpret as SDMMC_IDMALAR

ULA=B_0x0, ABR=B_0x0, ULS=B_0x0

Description

SDMMC IDMA linked list address register

Fields

IDMALA	Word aligned linked list item address offset
ABR	Acknowledge linked list buffer ready 0 (B_0x0): Loaded linked list buffer is not ready (this causes a linked list IDMA transfer error to be generated). 1 (B_0x1): Loaded linked list buffer ready acknowledge. Linked list buffer data are transfered by IDMA.
ULS	Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1) 0 (B_0x0): SDMMC_IDMABSIZER is not to be updated from next linked list table. 1 (B_0x1): SDMMC_IDMABSIZER is to be updated from next linked list table.
ULA	Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode) 0 (B_0x0): SDMMC_IDMALAR is not to be updated, last linked list item. 1 (B_0x1): SDMMC_IDMALAR is to be updated from linked list table.

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