PWRCTRL=B_0x0, VSWITCHEN=B_0x0, VSWITCH=B_0x0, DIRPOL=B_0x0
SDMMC power control register
| PWRCTRL | SDMMC state control bits 0 (B_0x0): After reset, Reset: the SDMMC is disabled and the clock to the Card is stopped, SDMMC_D[7:0], and SDMMC_CMD are HiZ and SDMMC_CK is driven low. 2 (B_0x2): Power-cycle, the SDMMC is disabled and the clock to the card is stopped, SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low. 3 (B_0x3): Power-on: the card is clocked, The first 74 SDMMC_CK cycles the SDMMC is still disabled. After the 74 cycles the SDMMC is enabled and the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are controlled according the SDMMC operation. |
| VSWITCH | Voltage switch sequence start 0 (B_0x0): Voltage switch sequence not started and not active. 1 (B_0x1): Voltage switch sequence started or active. |
| VSWITCHEN | Voltage switch procedure enable 0 (B_0x0): SDMMC_CK clock kept unchanged after successfully received command response. 1 (B_0x1): SDMMC_CK clock stopped after successfully received command response. |
| DIRPOL | Data and command direction signals polarity selection 0 (B_0x0): Voltage transceiver IOs driven as output when direction signal is low. 1 (B_0x1): Voltage transceiver IOs driven as output when direction signal is high. |